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d a t a sh eet product speci?cation supersedes data of 1999 sep 01 2003 jul 21 integrated circuits 74ahc273; 74ahct273 octal d-type flip-flop with reset; positive-edge trigger
2003 jul 21 2 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 features ideal buffer for mos microcontroller or memory common clock and master reset esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v. balanced propagation delays all inputs have schmitt-trigger actions inputs accepts voltages higher than v cc related products: C see 74ahc(t)377 for clock enable version C see 74ahc(t)373 for transparent latch version C see 74ahc(t)374 for 3-state version. for ahc only: operates with cmos input levels for ahct only: operates with ttl input levels specified from - 40 to +85 c and - 40 to +125 c. description the 74ahc/ahct273 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74ahc/ahct273 have eight edge-triggered, d-type flip-flops with individual d inputs and q outputs. the common clock (cp) and master reset ( mr) inputs load and reset (clear) all flip-flops simultaneously. the state of each d input, one set-up time before the low-to-high clock transition, is transferred to the corresponding output (qn) of the flip-flop. all outputs will be forced low independently of clock or data inputs by a low on the mr input. the device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. quick reference data ground = 0 v; t amb =25 c; t r =t f 3.0 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. the condition is v i = gnd to v cc symbol parameter conditions typical unit 74ahc273 74ahct273 t phl /t plh propagation delay c l = 15 pf; v cc =5v cp to qn 4.2 4.0 ns mr to qn 3.7 3.9 ns f max maximum clock frequency c l = 15 pf; v cc = 5 v 165 120 mhz c i input capacitance v i =v cc or gnd 3.0 3.0 pf c o output capacitance 4.0 4.0 pf c pd power dissipation capacitance c l = 50 pf; f = 1 mhz; notes 1 and 2 14.0 18.0 pf
2003 jul 21 3 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 function table see note 1. note 1. h = high voltage level; h = high voltage level one set-up time prior to the high-to-low cp transition; l = low voltage level; i = low voltage level one set-up time prior to the high-to-low cp transition; x = dont care; - = low-to-high transition. ordering information operating modes input output mr cp dn qn reset (clear) l x x l load 1 h - hh load 0 h - ll type number temperature range package pins package material code 74ahc273d - 40 to +125 c 20 so20 plastic sot163-1 74ahct273d - 40 to +125 c 20 so20 plastic sot163-1 74ahc273pw - 40 to +125 c 20 tssop20 plastic sot360-1 74ahct273pw - 40 to +125 c 20 tssop20 plastic sot360-1 74AHC273BQ - 40 to +125 c 20 dhvqfn20 plastic sot764-1 74ahct273bq - 40 to +125 c 20 dhvqfn20 plastic sot764-1 pinning pin symbol description 1 mr master reset input (active low) 2 q0 ?ip-?op output 3 d0 data input 4 d1 data input 5 q1 ?ip-?op output 6 q2 ?ip-?op output 7 d2 data input 8 d3 data input 9 q3 ?ip-?op output 10 gnd ground (0 v) 11 cp clock input (low-to-high; edge-triggered) 12 q4 ?ip-?op output 13 d4 data input 14 d5 data input 15 q5 ?ip-?op output 16 q6 ?ip-?op output 17 d6 data input 18 d7 data input 19 q7 ?ip-?op output 20 v cc supply voltage pin symbol description
2003 jul 21 4 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 fig.1 pin configuration so20 and tssop20. handbook, halfpage mr q0 d0 d1 q1 q2 d2 d3 q3 gnd v cc q7 d7 d6 q5 d5 q6 d4 q4 cp 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 273 mna459 fig.2 pin configuration dhvqfn20. handbook, halfpage 1 2 3 4 5 6 7 8 9 q0 d0 d1 q1 q2 d2 d3 q3 19 18 17 16 15 14 13 12 q7 d7 d6 q6 q5 d5 d4 q4 20 mr v cc 10 11 gnd top view cp gnd (1) mnb035 (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. fig.3 logic symbol. handbook, halfpage mna460 d0 d1 d2 d3 d4 d5 d6 d7 mr cp q0 q1 q2 q3 q4 q5 q6 q7 11 1 19 16 15 12 9 6 5 2 18 17 14 13 8 7 4 3 fig.4 iec logic symbol. handbook, halfpage mna461 19 16 15 12 9 6 5 11 c1 1 r 1d 2 18 17 14 13 8 7 4 3
2003 jul 21 5 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 fig.5 function diagram. handbook, halfpage mna462 ff1 to ff8 q0 q1 q2 q3 q4 q5 q6 q7 19 16 15 12 9 6 5 2 d0 d1 d2 d3 d4 d5 d6 d7 cp mr 18 11 1 17 14 13 8 7 4 3 fig.6 logic diagram. handbook, full pagewidth mna463 q0 d0 d ff1 q cp r d cp mr q1 d1 d ff2 q cp r d q2 d2 d ff3 q cp r d q3 d3 d ff4 q cp r d q4 d4 d ff5 q cp r d q5 d5 d ff6 q cp r d q6 d6 d ff7 q cp r d q7 d7 d ff8 q cp r d
2003 jul 21 6 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. for so20 packages: above 70 c the value of p d derates linearly with 8 mw/k. for tssop20 packages: above 60 c the value of p d derates linearly with 5.5 mw/k. for dhvqfn20 packages: above 60 c the value of p d derates linearly with 4.5 mw/k. symbol parameter conditions 74ahc 74ahct unit min. typ. max. min. typ. max. v cc supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 v v i input voltage 0 - 5.5 0 - 5.5 v v o output voltage 0 - v cc 0 - v cc v t amb ambient temperature see dc and ac characteristics per device - 40 +25 +85 - 40 +25 +85 c - 40 +25 +125 - 40 +25 +125 c t r , t f input rise and fall ratio v cc = 3.3 0.3 v -- 100 --- ns/v v cc =5 0.5 v -- 20 -- 20 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i ik input diode current v i < - 0.5 v; note 1 -- 20 ma i ok output diode current v o < - 0.5 v or v o >v cc + 0.5 v; note 1 - 20 ma i o output source or sink current v o = - 0.5 v to v cc + 0.5 v - 25 ma i cc , i gnd v cc or gnd current - 75 ma t stg storage temperature - 65 +150 c p d power dissipation t amb = - 40 to +125 c; note 2 - 500 mw
2003 jul 21 7 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 dc characteristics type 74ahc273 at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb =25 c v ih high-level input voltage 2.0 1.5 -- v 3.0 2.1 -- v 5.5 3.85 -- v v il low-level input voltage 2.0 -- 0.5 v 3.0 -- 0.9 v 5.5 -- 1.65 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 2.0 1.9 2.0 - v 3.0 2.9 3.0 - v 4.5 4.4 4.5 - v i o = - 4.0 ma 3.0 2.58 -- v i o = - 8.0 ma 4.5 3.94 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 2.0 - 0 0.1 v 3.0 - 0 0.1 v 4.5 - 0 0.1 v i o = 4.0 ma 3.0 -- 0.36 v i o = 8.0 ma 4.5 -- 0.36 v i li input leakage current v i =v cc or gnd 5.5 -- 0.1 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 4.0 m a c i input capacitance -- 310pf
2003 jul 21 8 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 t amb = - 40 to +85 c v ih high-level input voltage 2.0 1.5 -- v 3.0 2.1 -- v 5.5 3.85 -- v v il low-level input voltage 2.0 -- 0.5 v 3.0 -- 0.9 v 5.5 -- 1.65 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 2.0 1.9 -- v 3.0 2.9 -- v 4.5 4.4 -- v i o = - 4.0 ma 3.0 2.48 -- v i o = - 8.0 ma 4.5 3.8 -- v v ol low-level output voltage v i =v ih or v il v i o =50 m a 2.0 -- 0.1 v 3.0 -- 0.1 v 4.5 -- 0.1 v i o = 4.0 ma 3.0 -- 0.44 v i o = 8.0 ma 4.5 -- 0.44 v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 40 m a c i input capacitance --- 10 pf symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 jul 21 9 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 t amb = - 40 to +125 c v ih high-level input voltage 2.0 1.5 -- v 3.0 2.1 -- v 5.5 3.85 -- v v il low-level input voltage 2.0 -- 0.5 v 3.0 -- 0.9 v 5.5 -- 1.65 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 2.0 1.9 -- v 3.0 2.9 -- v 4.5 4.4 -- v i o = - 4.0 ma 3.0 2.40 -- v i o = - 8.0 ma 4.5 3.70 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 2.0 -- 0.1 v 3.0 -- 0.1 v 4.5 -- 0.1 v i o = 4.0 ma 3.0 -- 0.55 v i o = 8.0 ma 4.5 -- 0.55 v i li input leakage current v i =v cc or gnd 5.5 -- 2.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 80 m a c i input capacitance --- 10 pf symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 jul 21 10 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 type 74ahct273 at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb =25 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 4.5 4.4 4.5 - v i o = - 8.0 ma 4.5 3.94 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 4.5 - 0 0.1 v i o = 8.0 ma 4.5 -- 0.36 v i li input leakage current v i =v ih or v il 5.5 -- 0.1 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 4.0 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o =0 4.5 to 5.5 -- 1.35 ma c i input capacitance -- 310pf t amb = - 40 to +85 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 4.5 4.4 -- v i o = - 8.0 ma 4.5 3.8 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 4.5 -- 0.1 v i o = 8.0 ma 4.5 -- 0.44 v i li input leakage current v i =v ih or v il 5.5 -- 1.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 40 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o =0 4.5 to 5.5 -- 1.5 ma c i input capacitance --- 10 pf
2003 jul 21 11 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 t amb = - 40 to +125 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 4.5 4.4 -- v i o = - 8.0 ma 4.5 3.70 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 4.5 -- 0.1 v i o = 8.0 ma 4.5 -- 0.55 v i li input leakage current v i =v ih or v il 5.5 -- 2.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 80 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o =0 4.5 to 5.5 -- 1.5 ma c i input capacitance --- 10 pf symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 jul 21 12 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 ac characteristics type 74ahc273 ground = 0 v; t r =t f 3.0 ns. symbol parameter test conditions min. typ. max. unit waveforms c l (pf) v cc (v) t amb =25 c; note 1 t phl /t plh propagation delay cp to qn see figs 7 and 10 15 3.0 to 3.6 - 6.0 13.6 ns 4.5 to 5.5 - 4.2 9 ns 50 3.0 to 3.6 - 8.6 17.1 ns 4.5 to 5.5 - 6.0 11.0 ns t phl propagation delay mr to qn see figs 8 and 10 15 3.0 to 3.6 - 5.1 13.6 ns 4.5 to 5.5 - 3.7 8.5 ns 50 3.0 to 3.6 - 7.3 17.1 ns 4.5 to 5.5 - 5.3 10.5 ns f max maximum clock pulse frequency 15 3.0 to 3.6 75 120 - mhz 4.5 to 5.5 120 165 - mhz 50 3.0 to 3.6 50 75 - mhz 4.5 to 5.5 80 110 - mhz t w clock pulse width high or low see figs 7 and 10 50 3.0 to 3.6 5.0 -- ns 4.5 to 5.5 5.0 -- ns master reset pulse width low see figs 8 and 10 50 3.0 to 3.6 5.0 -- ns 4.5 to 5.5 5.0 -- ns t rem removal time mr to cp see figs 8 and 10 50 3.0 to 3.6 2.5 -- ns 4.5 to 5.5 2.0 -- ns t su set-up time dn to cp see figs 9 and 10 50 3.0 to 3.6 3.0 -- ns 4.5 to 5.5 3.0 -- ns t h hold time dn to cp see figs 9 and 10 50 3.0 to 3.6 1.0 -- ns 4.5 to 5.5 1.0 -- ns
2003 jul 21 13 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 t amb = - 40 to +85 c t phl /t plh propagation delay cp to qn see figs 7 and 10 15 3.0 to 3.6 1.0 - 16.0 ns 4.5 to 5.5 1.0 - 10.5 ns 50 3.0 to 3.6 1.0 - 19.5 ns 4.5 to 5.5 1.0 - 12.5 ns t phl propagation delay mr to qn see figs 8 and 10 15 3.0 to 3.6 1.0 - 16.0 ns 4.5 to 5.5 1.0 - 10.0 ns 50 3.0 to 3.6 1.0 - 19.5 ns 4.5 to 5.5 1.0 - 12.0 ns f max maximum clock pulse frequency 15 3.0 to 3.6 65 -- mhz 4.5 to 5.5 100 -- mhz 50 3.0 to 3.6 45 -- mhz 4.5 to 5.5 70 -- mhz t w clock pulse width high or low see figs 7 and 10 50 3.0 to 3.6 6.5 -- ns 4.5 to 5.5 5.0 -- ns master reset pulse width low see figs 8 and 10 50 3.0 to 3.6 6.0 -- ns 4.5 to 5.5 5.0 -- ns t rem removal time mr to cp see figs 8 and 10 50 3.0 to 3.6 2.5 -- ns 4.5 to 5.5 2.0 -- ns t su set-up time dn to cp see figs 9 and 10 50 3.0 to 3.6 3.0 -- ns 4.5 to 5.5 3.0 -- ns t h hold time dn to cp see figs 9 and 10 50 3.0 to 3.6 1.0 -- ns 4.5 to 5.5 1.0 -- ns symbol parameter test conditions min. typ. max. unit waveforms c l (pf) v cc (v)
2003 jul 21 14 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 note 1. typical values are measured at v cc = 3.3 v for v cc = 3.0 to 3.6 v and at v cc = 5.0 v for v cc = 4.5 to 5.5 v. t amb = - 40 to +125 c t phl /t plh propagation delay cp to qn see figs 7 and 10 15 3.0 to 3.6 1.0 - 17.0 ns 4.5 to 5.5 1.0 - 11.5 ns 50 3.0 to 3.6 1.0 - 21.5 ns 4.5 to 5.5 1.0 - 14.0 ns t phl propagation delay mr to qn see figs 8 and 10 15 3.0 to 3.6 1.0 - 17.0 ns 4.5 to 5.5 1.0 - 11.0 ns 50 3.0 to 3.6 1.0 - 21.5 ns 4.5 to 5.5 1.0 - 13.5 ns f max maximum clock pulse frequency 15 3.0 to 3.6 65 -- mhz 4.5 to 5.5 100 -- mhz 50 3.0 to 3.6 45 -- mhz 4.5 to 5.5 70 -- mhz t w clock pulse width high or low see figs 7 and 10 50 3.0 to 3.6 6.5 -- ns 4.5 to 5.5 5.0 -- ns master reset pulse width low see figs 8 and 10 50 3.0 to 3.6 6.0 -- ns 4.5 to 5.5 5.0 -- ns t rem removal time mr to cp see figs 8 and 10 50 3.0 to 3.6 2.5 -- ns 4.5 to 5.5 2.0 -- ns t su set-up time dn to cp see figs 9 and 10 50 3.0 to 3.6 3.0 -- ns 4.5 to 5.5 3.0 -- ns t h hold time dn to cp see figs 9 and 10 50 3.0 to 3.6 1.0 -- ns 4.5 to 5.5 1.0 -- ns symbol parameter test conditions min. typ. max. unit waveforms c l (pf) v cc (v)
2003 jul 21 15 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 type 74ahct273 ground = 0 v; t r =t f 3.0 ns. symbol parameter test conditions min. typ. max. unit waveforms c l (pf) v cc (v) t amb =25 c; note 1 t phl /t plh propagation delay cp to qn see figs 7 and 10 15 4.5 to 5.5 - 4.0 7.5 ns 50 4.5 to 5.5 - 5.8 9.2 ns t phl propagation delay mr to qn see figs 8 and 10 15 4.5 to 5.5 - 3.9 10.0 ns 50 4.5 to 5.5 - 5.6 11.0 ns f max maximum clock pulse frequency 15 4.5 to 5.5 75 120 - mhz 50 4.5 to 5.5 50 75 - mhz t w clock pulse width high or low see figs 7 and 10 50 4.5 to 5.5 5.0 -- ns master reset pulse width low see figs 8 and 10 50 4.5 to 5.5 5.0 -- ns t rem removal time mr to cp see figs 8 and 10 50 4.5 to 5.5 2.5 -- ns t su set-up time dn to cp see figs 9 and 10 50 4.5 to 5.5 3.0 -- ns t h hold time dn to cp see figs 9 and 10 50 4.5 to 5.5 1.0 -- ns t amb = - 40 to +85 c t phl /t plh propagation delay cp to qn see figs 7 and 10 15 4.5 to 5.5 1.0 - 8.8 ns 50 4.5 to 5.5 1.0 - 10.5 ns t phl propagation delay mr to qn see figs 8 and 10 15 4.5 to 5.5 1.0 - 11.6 ns 50 4.5 to 5.5 1.0 - 12.6 ns f max maximum clock pulse frequency 15 4.5 to 5.5 65 -- mhz 50 4.5 to 5.5 45 -- mhz t w clock pulse width high or low see figs 7 and 10 50 4.5 to 5.5 6.5 -- ns master reset pulse width low see figs 8 and 10 50 4.5 to 5.5 6.0 -- ns t rem removal time mr to cp see figs 8 and 10 50 4.5 to 5.5 2.5 -- ns t su set-up time dn to cp see figs 9 and 10 50 4.5 to 5.5 3.0 -- ns t h hold time dn to cp see figs 9 and 10 50 4.5 to 5.5 1.0 -- ns
2003 jul 21 16 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 note 1. all typical values are measured at v cc = 5.0 v. t amb = - 40 to +125 c t phl /t plh propagation delay cp to qn see figs 7 and 10 15 4.5 to 5.5 1.0 - 9.5 ns 50 4.5 to 5.5 1.0 - 11.5 ns t phl propagation delay mr to qn see figs 8 and 10 15 4.5 to 5.5 1.0 - 12.5 ns 50 4.5 to 5.5 1.0 - 14.0 ns f max maximum clock pulse frequency 15 4.5 to 5.5 65 -- mhz 50 4.5 to 5.5 45 -- mhz t w clock pulse width high or low see figs 7 and 10 50 4.5 to 5.5 6.5 -- ns master reset pulse width low see figs 8 and 10 50 4.5 to 5.5 6.0 -- ns t rem removal time mr to cp see figs 8 and 10 50 4.5 to 5.5 2.5 -- ns t su set-up time dn to cp see figs 9 and 10 50 4.5 to 5.5 3.0 -- ns t h hold time dn to cp see figs 9 and 10 50 4.5 to 5.5 1.0 -- ns t phl /t plh propagation delay cp to qn see figs 7 and 10 15 4.5 to 5.5 1.0 - 9.5 ns symbol parameter test conditions min. typ. max. unit waveforms c l (pf) v cc (v)
2003 jul 21 17 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 ac waveforms fig.7 the clock (cp) to output (qn) propagation delays, the clock pulse width output transition times and the maximum clock pulse frequency. family v i v m input v m output ahc gnd to v cc 0.5v cc 0.5v cc ahct gnd to 3.0 v 1.5 v 0.5v cc handbook, full pagewidth mnb036 t phl t plh t w 1/f max v m v m cp input qn output gnd v i fig.8 the master reset ( mr) pulse width, the master reset to output (qn) propagation delays and master reset to clock (cp) removal time. family v i v m input v m output ahc gnd to v cc 0.5v cc 0.5v cc ahct gnd to 3.0 v 1.5 v 0.5v cc handbook, full pagewidth mna464 mr input cp input qn output t plh t w t rem v m v i gnd v i gnd v m v m
2003 jul 21 18 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 handbook, full pagewidth mna202 gnd gnd t h t h t su t su v m v m v m v i v oh v ol v i qn output cp input dn input fig.9 the data set-up and hold times for the data input (dn). the shaded areas indicate when the input is permitted to change for predicable output performance. family v i v m input v m output ahc gnd to v cc 0.5v cc 0.5v cc ahct gnd to 3.0 v 1.5 v 0.5v cc fig.10 load circuitry for switching times. handbook, full pagewidth open gnd v cc v cc v i v o mna183 d.u.t. c l r t r l = 1 k w pulse generator s1 test s1 t plh /t phl open t plz /t pzl v cc t phz /t pzh gnd definitions for test circuit. c l = load capacitance including jig and probe capacitance (see chapter ac characteristics). r l = load resistor. r t = termination resistance should be equal to the output impedance z o of the pulse generator.
2003 jul 21 19 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
2003 jul 21 20 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
2003 jul 21 21 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764-1 dhvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
2003 jul 21 22 philips semiconductors product speci?cation octal d-type ?ip-?op with reset; positive-edge trigger 74ahc273; 74ahct273 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/02/pp 23 date of release: 2003 jul 21 document order number: 9397 750 11222

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